1. Field of the Invention
This invention relates to the chip layout of a semiconductor memory device, and more particularly to the pattern layout of power source lines in a semiconductor memory device.
2. Description of the Related Art
Various configurations of the chip layout in a semiconductor memory device such as a dynamic RAM or static RAM are disclosed in "ELECTRONIC PARTS AND MATERIALS" May 1983, pp 123-129 "Noticeable Articles in ISSCC'83" issued from the Industry Researching Society, for example.
In recent years, the integration density of the semiconductor memory device has been markedly increased, and with the formation of the semiconductor memory device of even higher integration density, the size of memory cells has been reduced. Since the thickness of the insulation film of the miniaturized memory cell is reduced, the breakdown voltage thereof becomes lower and the reliability thereof becomes lower. In order to ensure the high reliability of the memory cell, attempts have been made to lower the power source potential of a memory area and a circuit used for the memory area. That is, the power source potential supplied to the chip from the exterior is set to 5V, for example, which is the same level as that used at present and the power source potential for the memory area and the circuit used for the memory area is set to a potential level (for example, 3.OV to 3.5V) which is lower than 5V. Therefore, even if a thin insulation film is used in the miniaturized memory cell, the dielectric breakdown can be suppressed and the reliability can be kept high.
However, in a device formed based on the above method, three power source lines, that is, a power source line for applying 5V to the chip, a power source line applied with a voltage less than 5V and a power source line applied with a ground potential are required. As a result, the number of power source lines in the above device is increased in comparison with a case of the conventional device in which only a 5V power source is used. Further, since not only a peripheral circuit used for the memory area but also a peripheral circuit used for the external portion of the chip are provided in the chip, a useless area may be provided on the chip and the chip area may be increased unless special and careful attention is given to the arrangement of the peripheral circuits and the laying of the power source lines.